/****************************************************************************
*Sample discrete
******************************************************************************/
/******************************************************************************
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*******************************************************************************
*******************************************************************************
* Module: discrete.c
*******************************************************************************
* Author(s):
*******************************************************************************
* Description: This module is responsible for discrete software
*******************************************************************************
* Revision history:
* Revision date Initials Comments
* -----------------------------------------------------------------------------
*******************************************************************************
*$Header$
*******************************************************************************
*$Log$
*******************************************************************************
*$NoKeywords$
*/
#define NOGPIOPINS 80
U32 digitalIO1[NOGPIOPINS],digitalIO2[NOGPIOPINS],digitalIO3[NOGPIOPINS],debounced_raw_discrete_data[NOGPIOPINS];
/* for this application there are only 5 discrete inputs RA0,RA1,RA2,RA3,RA4 */
enum digital
{
D_RA0 30,
D_RA1 29,
D_RA2 28,
D_RA3 27,
D_RA4 34,
D_RA5 33,
D_RB0 58,
D_RB1 57,
D_RB2 56,
D_RB3 55,
D_RB4 54,
D_RB5 53,
D_RB6 52,
D_RB7 47,
D_RC0 36,
D_RC1 35,
D_RC2 43,
D_RC3 44,
D_RC4 45,
D_RC5 46,
D_RC6 37,
D_RC7 38,
D_RD0 72,
D_RD1 69,
D_RD2 68,
D_RD3 67,
D_RD4 66,
D_RD5 65,
D_RD6 64,
D_RD7 63,
D_RE0 4,
D_RE1 3,
D_RE2 78,
D_AD11 77,
D_AD12 76,
D_AD13 75,
D_AD14 74,
D_AD15 73,
D_RF0 24,
D_RF1 23,
D_RF2 18,
D_RF3 17,
D_RF4 16,
D_RF5 15,
D_RF6 14,
D_RF7 11
};
void read_discrete_input(U32 pinno)
{
switch(pinno)
{
case 30:
digitalIO1[D_RA0]=RA0;
digitalIO2[D_RA0]=RA0;
digitalIO3[D_RA0]=RA0;
break;
case 29:
digitalIO1[D_RA1]=RA1;
digitalIO2[D_RA1]=RA1;
digitalIO3[D_RA1]=RA1;
break;
case 28:
digitalIO1[D_RA2]=RA2;
digitalIO2[D_RA2]=RA2;
digitalIO3[D_RA2]=RA2;
break;
case 27:
digitalIO[D_RA3]=RA3;
break;
case 34:
digitalIO[D_RA4]=RA4;
break;
case 33:
digitalIO[D_RA5]=RA5;
break;
case 58:
digitalIO[D_RB0]=RB0;
break;
case 57:
digitalIO[D_RB1]=RB1;
break;
case 56:
digitalIO[D_RB6]=RB6;
break;
case 55:
digitalIO[D_RB3]=RB3;
break;
case 54:
digitalIO[D_RB4]=RB4;
break;
case 53:
digitalIO[D_RB5]=RB5;
break;
case 52:
digitalIO[D_RB6]=RB6;
break;
case 36:
digitalIO[D_RC0]=RC0;
break;
case 35:
digitalIO[D_RC1]=RC1;
break;
case 43:
digitalIO[D_RC2]=RC2;
break;
case 44:
digitalIO[D_RC3]=Rc3;
break;
case 45:
digitalIO[D_RC4]=RC4;
break;
case 46:
digitalIO[D_RC5]=RC5;
break;
case 37:
digitalIO[D_RC6]=RC6;
break;
case 72:
digitalIO[D_RD0]=RD0;
break;
case 69:
digitalIO[D_RD1]=RD1;
break;
case 68:
digitalIO[D_RD2]=RD2;
break;
case 67:
digitalIO[D_RD3]=RD3;
break;
case 66:
digitalIO[D_RD4]=RD4;
break;
case 58:
digitalIO[D_RB0]=RB0;
break;
case 65:
digitalIO[D_RD5]=RD5;
break;
case 64:
digitalIO[D_RD6]=RD6;
break;
case 63:
digitalIO[D_RD7]=RD7;
break;
case 58:
digitalIO[D_RB0]=RB0;
break;
case 58:
digitalIO[D_RB0]=RB0;
break;
case 58:
digitalIO[D_RB0]=RB0;
break;
case 4:
digitalIO[D_RE0]=RE0;
break;
case 3:
digitalIO[D_RE1]=RE1;
break;
case 78:
digitalIO[D_RE2]=RE2;
break;
case 77:
digitalIO[D_AD11]=AD11;
break;
case 76:
digitalIO[D_AD12]=AD12;
break;
case 75:
digitalIO[D_AD13]=AD13;
break;
case 74:
digitalIO[D_AD14]=AD14;
break;
case 73:
digitalIO[D_AD15]=ad15;
break;
case 24:
digitalIO[D_RF0]=RF0;
break;
case 23:
digitalIO[D_RF1]=RF1;
break;
case 18:
digitalIO[D_RF2]=RF2;
break;
case 17:
digitalIO[D_RF3]=RF3;
break;
case 16:
digitalIO[D_RF4]=RF4;
break;
case 15:
digitalIO[D_RF5]=RF5;
break;
case 14:
digitalIO[D_RF6]=RF6;
break;
case 11:
digitalIO[D_RF7]=RF7;
break;
default:
break;
}
}
void write_discrete_output(U32 pinno)
{
switch(pinno)
{
case 30:
RA0=digitalIO[D_RA0];
break;
case 29:
RA1=digitalIO[D_RA1];
break;
case 28:
RA2=digitalIO[D_RA2];
break;
case 27:
RA3=digitalIO[D_RA3];
break;
case 34:
RA4=digitalIO[D_RA4];
break;
case 33:
RA5=digitalIO[D_RA5];
break;
case 58:
RB0=digitalIO[D_RB0];
break;
case 57:
RB1=digitalIO[D_RB1];
break;
case 56:
RB6=digitalIO[D_RB6];
break;
case 55:
RB3=digitalIO[D_RB3];
break;
case 54:
RB4=digitalIO[D_RB4];
break;
case 53:
RB5=digitalIO[D_RB5];
break;
case 52:
RB6=digitalIO[D_RB6];
break;
case 36:
RC0=digitalIO[D_RC0];
break;
case 35:
RC1=digitalIO[D_RC1];
break;
case 43:
RC2=digitalIO[D_RC2];
break;
case 44:
RC3=digitalIO[D_RC3];
break;
case 45:
RC4=digitalIO[D_RC4];
break;
case 46:
RC5=digitalIO[D_RC5];
break;
case 37:
RC6=digitalIO[D_RC6];
break;
case 72:
RD0=digitalIO[D_RD0];
break;
case 69:
RD1=digitalIO[D_RD1];
break;
case 68:
RD2=digitalIO[D_RD2];
break;
case 67:
RD3=digitalIO[D_RD3];
break;
case 66:
RD4=digitalIO[D_RD4];
break;
case 58:
RB0=digitalIO[D_RB0];
break;
case 65:
RD5=digitalIO[D_RD5];
break;
case 64:
RD6=digitalIO[D_RD6];
break;
case 63:
RD7=digitalIO[D_RD7];
break;
case 4:
RE0=digitalIO[D_RE0]
break;
case 3:
RE1=digitalIO[D_RE1];
break;
case 78:
RE2=digitalIO[D_RE2];
break;
case 77:
AD11=digitalIO[D_AD11];
break;
case 76:
AD12=digitalIO[D_AD12];
break;
case 75:
AD13=digitalIO[D_AD13];
break;
case 74:
AD14=digitalIO[D_AD14];
break;
case 73:
Ad15=digitalIO[D_AD15];
break;
case 24:
RF0=digitalIO[D_RF0];
break;
case 23:
RF1=digitalIO[D_RF1];
break;
case 18:
RF2=digitalIO[D_RF2];
break;
case 17:
RF3=digitalIO[D_RF3];
break;
case 16:
RF4=digitalIO[D_RF4];
break;
case 15:
RF5=digitalIO[D_RF5];
break;
case 14:
RF6=digitalIO[D_RF6];
break;
case 11:
RF7=digitalIO[D_RF7];
break;
default:
break;
}
}
void GPIO_DEBOUNCED_DATA(void)
{
/* DEBOUNCE 2 of 3 voting */
for (i=0;i<NOGPIOPINS;i++)
{
if ((digitalIO1[i]==digitalIO2[i])
&& (digitalIO2[i]==digitalIO3[i]))
debounced_raw_discrete_data[i]=digitalIO1[i];
if ((digitalIO2[i]==digitalIO3[i])
&& (digitalIO2[i]==digitalIO1[i]))
debounced_raw_discrete_data[i]=digitalIO2[i];
if ((digitalIO3[i]==digitalIO1[i])
&& (digitalIO3[i]==digitalIO2[i]))
debounced_raw_discrete_data[i]=digitalIO3[i];
}
}
/* configure ADC channels 4,,12,13,10,11 as inputs using data direction registers set 5 discrete inputs RA0,RA1,RA2,RA3,RA4*/
void port_init(void)
{
PORTA=0x0;
LATA=0x0;
TRISA=0x2F;
PORTB=0x0;
LATB=0x0;
TRISB=0x3F;
PORTC=0x0;
LATC=0x0;
TRISC=0x00;
PORTD=0x0;
LATD=0x0;
TRISD=0x00;
PORTE=0x0;
LATE=0x0;
TRISE=0x00;
PORTF=0x0;
LATF=0x0;
TRISF=0x00;
PORTG=0x0;
LATG=0x0;
TRISG=0x00;
PORTH=0x0;
LATH=0x0;
TRISH=0xCF;
PORTI=0x0;
LATI=0x0;
TRISI=0x2F;
PORTJ=0x0;
LATJ=0x0;
TRISJ=0x2F;
}